An IC is normally created from a generally flat semiconductor chip by establishing the circuit elements that implement the circuit's function, establishing an organization for the circuit elements along one surface of the chip, generating masks that represent the organization of the circuit elements, and fabricating the IC using the masks. The process of determining the organization of the circuit elements along the chip's surface is commonly referred to as laying out the IC. The layout design can be accomplished in various ways.
In the full-custom design approach, the circuit elements and their interconnections are laid out manually. For a specific fabrication process, an IC laid out according to the full-custom approach typically achieves the highest speed and occupies the smallest chip area among today's IC layout methodologies. However, the full-custom approach is labor intensive and thus very expensive.
The layout design cost can be reduced by using various automatic or semi-automatic techniques to decrease the layout time. For example, consider an IC in which many process operations are to be repeated largely in parallel. Such an IC can be laid out as a multi-bit datapath in which each bit of the datapath is processed along a datapath slice, commonly referred to as a bitslice, that is largely repeated for each other bit. Control logic outside the datapath is used to control information processing along the datapath. Although the datapath is typically designed and laid out manually, the layout cost is reduced by implementing the control logic with a gate array using automatic place-and-route software to define the circuit interconnections.
Referring to the drawings, FIG. 1 illustrates the circuitry details for a typical circuit element 10 implemented with a complementary metal-oxide semiconductor ("CMOS") gate array. Circuit element 10 is a two-input multiplexer-latch combination consisting of transmission gates 11-14 and CMOS inverters 15-17. Dependent on the values of complementary control signal pairs S0 and S0, S1 and S1, and T and T, either input data signal D0 or input data signal D1 is latched to produce true data output signal Q.
In a CMOS gate array, the insulated-gate field-effect transistors ("FETs") all typically have approximately the same current-carrying capability. Consequently, many of the circuit elements, such as multiplexer-latch combination 10, laid out with a CMOS gate array employ a relatively large number of FETs. In particular, each transmission gate and CMOS inverter contains two FETs, resulting in a total of 14 FETs in circuit element 10. While using a CMOS gate array to implement the control logic for the datapath reduces the layout design time, the high number of transistors increases the chip area and leads to a loss in speed. Also, gate utilization is typically well below 100%, leading to a further increase in chip area.
Due to the high chip area and low speed, CMOS gate arrays are unattractive for laying out datapath sections of ICs. However, designing the datapath manually is time consuming and expensive. Furthermore, circuit errors in a custom-designed datapath often require a large amount of layout redesign and associated expense. It would be desirable to have a methodology by which the layout for an IC, especially the datapath of an IC, can be produced at relatively low cost without incurring the speed loss and area increase associated with the CMOS gate array approach. In would also be desirable if correction of circuit design errors in such a layout methodology could be performed without requiring substantial layout redesign and attendant cost.